The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
With small feature sizes in advanced technology nodes, control of semiconductor fabrication processes faces many challenges. In a semiconductor fabrication facility, monitoring the results of process steps has become critical. Misalignment, lithography defects, and tool drift can cause unsatisfactory results in a process even after a period of time with satisfactory results. Overlay monitoring and control becomes crucial to minimize overlay errors. Non-systematic imperfections, such as dust particles, overlay mark asymmetry, or overlay mark damages, may cause large overlay errors, often referred to as “noise.” Noise degrades accuracy in overlay control. It is desirable to have techniques that can reduce or filter out the noise during process overlay control.